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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max1108/max1109 low-power, 8-bit, dual-channel, analog-to-digital converters (adcs) feature an internal track/hold (t/h) voltage reference, clock, and serial inter- face. the max1108 is specified from +2.7v to +3.6v and consumes only 105?. the max1109 is specified from +4.5v to +5.5v and consumes only 130?. the analog inputs are software configurable, allowing unipolar/bipolar and single-ended/differential operation; battery monitor- ing capability is also included. the full-scale analog input range is determined by the internal reference of +2.048v (max1108) or +4.096v (max1109), or by an externally applied reference rang- ing from 1v to v dd . the max1108/max1109 also feature a software power-down mode that reduces power con- sumption to 0.5? when the device is not in use. the 4-wire serial interface directly connects to spi, qspi, and microwire devices without external logic. conversions up to 50ksps are performed using either the internal clock or an external serial-interface clock. the max1108 and max1109 are available in a 10-pin ?ax package with a footprint that is just 20% of an 8-pin plastic dip. applications portable data logging hand-held measurement devices medical instruments system diagnostics solar-powered remote systems 4?0ma-powered remote systems receive-signal strength indicators features ? single supply: +2.7v to +3.6v (max1108) +4.5v to +5.5v (max1109) ? low power: 105? at +3v and 50ksps 0.5? in power-down mode ? software-configurable unipolar or bipolar inputs ? input voltage range: 0 to v dd ? internal track/hold ? internal reference: +2.048v (max1108) +4.096v (max1109) ? reference input range: 1v to v dd ? spi/qspi/microwire-compatible serial interface ? v dd monitoring mode ? small 10-pin ?ax package max1108/max1109 single-supply, low-power, 2-channel, serial 8-bit adcs ________________________________________________________________ maxim integrated products 1 1 2 3 4 5 10 9 8 7 6 sclk dout din cs gnd ch1 ch0 v dd max1108 max1109 m max top view com ref input shift register control logic t/h sar internal oscillator output shift register v dd analog input mux internal reference dout sclk din ch0 com ref ch1 cs gnd charge redistribution dac max1108 max1109 functional diagram 19-1399; rev 0; 10/98 pin configuration ordering information part max1108 cub max1108eub -40? to +85? 0? to +70? temp. range pin-package 10 ?ax 10 ?ax max1109 cub max1109eub -40? to +85? 0? to +70? 10 ?ax 10 ?ax spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax1108 (v dd = +2.7v to +3.6v; unipolar input mode; com = gnd, f sclk = 500khz, external clock mode (50% duty cycle); 10 clocks/conver - sion cycle (50ksps); 1 f capacitor at ref, external +2.048v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd .............................................................. -0.3v to +6v ch0, ch1, com, ref, dout to gnd ....... -0.3v to (v dd + 0.3v) din, sclk, cs to gnd ............................................ -0.3v to +6v continuous power dissipation (t a = +70 c) 10-pin max (derate 5.6mw/ c above +70 c) ............ 444mw operating temperature ranges max110_cub ...................................................... 0 c to +70 c max110_eub ................................................... -40 c to +85 c storage temperature range ............................. -65 c to +150 c lead temperature (soldering, 10sec) ............................. +300 c v dd = 2.7v to 3.6v v dd = 5.5v (note 2) no missing codes over temperature conditions 0.15 0.5 bits 8 resolution lsb 0.2 inl relative accuracy (note 1) lsb 1 dnl differential nonlinearity units min typ max symbol parameter v dd = 5.5v (note 2) v dd = 2.7v to 3.6v lsb 0.5 offset error 0.2 1 lsb 1 gain error (note 3) ppm/ c 0.8 gain temperature coefficient t a = t min to t max t a = +25 c mv 50 v dd / 2 sampling accuracy db 49 sinad signal-to-noise plus distortion db -70 thd total harmonic distortion (up to the 5th harmonic) lsb 0.5 tue total unadjusted error 1 lsb 0.1 channel-to-channel offset matching -3db rolloff unipolar input, v com = 0 mhz 0.8 full-power bandwidth mhz 1.5 bw -3db small-signal bandwidth 0 v ref input voltage range (note 4) db 68 sfdr spurious-free dynamic range bipolar input, v com or v ch1 = v ref / 2, referenced to com or ch1 v v ref / 2 v ch_ pf 18 c in input capacitance on/off-leakage current, v com or v ch = 0 or v dd a 0.01 1 multiplexer leakage current dc accuracy dynamic performance (10khz sine-wave input, 2.048vp-p, 50ksps, 500khz external clock) analog inputs
a max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs _______________________________________________________________________________________ 3 electrical characteristics?ax1108 (continued) (v dd = +2.7v to +3.6v; unipolar input mode; com = gnd, f sclk = 500khz, external clock mode (50% duty cycle); 10 clocks/conver - sion cycle (50ksps); 1 f capacitor at ref, external +2.048v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) conditions units min typ max symbol parameter external clock, 500khz, 10 sclks/conv internal clock external clock, 2mhz s 20 t conv conversion time (note 5) 35 s 1 t acq track/hold acquisition time ps <50 aperture jitter ns 10 aperture delay khz 400 internal clock frequency (note 6) 0 to 0.5ma (note 7) ppm/ c 50 ref tempco a 150 i refsc ref short-circuit current mv 2.5 load regulation khz 50 500 v 1.968 2.048 2.128 v ref output voltage +2.048v at ref, full scale, 500khz external clock a 1 20 input current v 2.7 3 5.5 v dd supply voltage power down, v dd = 2.7v to 3.6v full-scale input, v dd = 2.7v to 3.6v 0.5 2.5 i dd mv 0.4 4 psr power-supply rejection (note 9) v dd = 2.7v to 3.6v, c l = 10pf v dd = 5.5v, c l = 10pf 105 250 130 f 1 capacitive bypass at ref v 0.2 v hyst input hysteresis v 0.8 v il threshold voltage low a 1 i ih input current high v dd 3.6v v dd > 3.6v v 2 v 3 v ih threshold voltage high mhz 2 external clock frequency range v 1.0 v dd + 0.05 input voltage range a 1 i il input current low pf 15 c in input capacitance for data transfer only internal reference external reference 70 internal reference external reference 95 a supply current (notes 2, 8) track/hold internal reference external reference power requirements digital inputs (din, sclk , and cs )
wake-up time max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 4 _______________________________________________________________________________________ cs = v dd cs = v dd pf 15 c out three-state output capacitance a 0.01 10 i l three-state leakage current figure 1, c load = 100pf figure 1, c load = 100pf figure 2, c load = 100pf ns 240 t dv cs fall to output enable ns conditions 20 200 t do sclk fall to output data valid ns 240 t tr cs rise to output disable ns 100 t ds din to sclk setup time s 1.0 t acq acquisition time ns 0 t dh din to sclk hold time external reference internal reference (note 10) s 20 ns 200 t cl sclk pulse width low ms 12 t wake wake-up time ns 0 t csh cs to sclk rise hold ns 100 t css cs to sclk rise setup ns 200 t ch sclk pulse width high units min typ max symbol parameter i sink = 5ma i source = 0.5ma i sink = 16ma v 0.4 v v dd - 0.5 v oh output high voltage v 0.8 v ol output low voltage electrical characteristics?ax1108 (continued) (v dd = +2.7v to +3.6v; unipolar input mode; com = gnd, f sclk = 500khz, external clock mode (50% duty cycle); 10 clocks/conver - sion cycle (50ksps); 1 f capacitor at ref, external +2.048v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) electrical characteristics?ax1109 (v dd = +4.5v to +5.5v; unipolar input mode; com = gnd, f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1 f capacitor at ref, external +4.096v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) v dd = 4.5v to 5.5v lsb offset error 0.2 1 lsb 1 v dd = 4.5v to 5.5v no missing codes over temperature gain error (note 3) ppm/ c 0.8 conditions gain temperature coefficient t a = t min to t max t a = +25 c mv 50 v dd / 2 sampling accuracy lsb 0.5 tue total unadjusted error 1 lsb 0.1 channel-to-channel offset matching 0.15 0.5 bits 8 resolution lsb inl relative accuracy (note 1) lsb 1 dnl differential nonlinearity units min typ max symbol parameter digital output (dout) timing characteristics (figures 8, 9, and 10) dc accuracy
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs _______________________________________________________________________________________ 5 electrical characteristics?ax1109 (continued) (v dd = +4.5v to +5.5v; unipolar input mode; com = gnd, f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1 f capacitor at ref, external +4.096v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) ps <50 aperture jitter ns 10 aperture delay khz 400 internal clock frequency 0 to 0.5ma (note 7) ppm/ c 50 ref tempco ma conditions 5 i refsc ref short-circuit current mv 2.5 load regulation khz 50 500 v v 3.936 4.096 4.256 v ref output voltage +4.096v at ref, full scale, 500khz external clock a 1 20 input current 1.0 v dd + 0.05 input voltage range f 1 capacitive bypass at ref units min typ max symbol parameter external clock, 2mhz db sinad signal-to-noise plus distortion 49 s 1 t acq track/hold acquisition time external clock, 500khz, 10 sclks/conv internal clock s 20 t conv conversion time (note 5) 35 sfdr spurious free dynamic range db db 68 thd total harmonic distortion (up to the 5th harmonic) -70 full-power bandwidth mhz unipolar input, v com = 0 0 v ref -3db rolloff mhz 0.8 bw -3db small-signal bandwidth 1.5 v ch_ input voltage range (note 4) v multiplexer leakage current a on/off-leakage current, v ch = 0 or v dd 0.01 1 pf c in input capacitance 18 bipolar input, v com or v ch1 = v ref / 2, referenced to com or ch1 v ref / 2 mhz 2 external clock frequency range dynamic performance (10khz sine-wave input, 4.096vp-p, 50ksps, 500khz external clock) analog inputs track/hold external reference internal reference for data transfer only
a max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 6 _______________________________________________________________________________________ electrical characteristics?ax1109 (continued) (v dd = +4.5v to +5.5v; unipolar input mode; com = gnd, f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1 f capacitor at ref, external +4.096v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) cs = v dd cs = v dd pf 15 c out three-state output capacitance a 0.01 10 i l three-state leakage current figure 1, c load = 100pf figure 1, c load = 100pf figure 2, c load = 100pf ns 240 t dv cs fall to output enable ns conditions 20 200 t do sclk fall to output data valid ns 240 t tr cs rise to output disable ns 100 t ds din to sclk setup time s 1.0 t acq acquisition time ns 0 t dh din to sclk hold time units min typ max symbol parameter i sink = 5ma i sink = 16ma 0.4 v 4.5 5 5.5 v dd supply voltage v 0.8 v ol output low voltage v dd = 4.5v to 5.5v, c l = 10pf, full-scale input 130 250 power down, v dd = 4.5v to 5.5v 0.5 2.5 95 external reference = +4.096v, full-scale input, v dd = 4.5v to 5.5v mv 0.4 4 psr power-supply rejection (note 9) v 0.2 v hyst input hysteresis v 0.8 v il threshold voltage low v 3 v ih threshold voltage high a 1 i ih input current high pf 15 c in input capacitance i source = 0.5ma v v dd - 0.5 v oh output high voltage a 1 i il input current low i dd a supply current (notes 2, 8) internal reference external reference power requirements digital inputs (din, sclk , and cs ) digital output (dout) timing characteristics (figures 8, 9, and 10)
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs _______________________________________________________________________________________ 7 electrical characteristics?ax1109 (continued) (v dd = +4.5v to +5.5v; unipolar input mode; com = gnd, f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1 f capacitor at ref, external +4.096v reference at ref; t a = t min to t max ; unless otherwise noted. typical values are at t a = +25 c.) conditions external reference internal reference (note 10) s 20 ns 200 t cl sclk pulse width low ms 12 t wake wake-up time ns 0 t csh cs to sclk rise hold ns 100 t css cs to sclk rise setup ns 200 t ch sclk pulse width high units min typ max symbol parameter note 1: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 2: see typical operating characteristics . note 3: v ref = +2.048v (max1108), v ref = +4.096v (max1109), offset nulled. note 4: common-mode range (ch0, ch1, com) gnd to v dd . note 5: conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle (figures 6 and 8). note 6: ref supplies typically 2.5ma under normal operating conditions. note 7: external load should not change during the conversion for specified accuracy. note 8: power consumption with cmos levels. note 9: measured as ? v fs (2.7v) - v fs (3.6v) ? for max1108, and measured as ? v fs (4.5v) - v fs (5.5v) ? for max1109. note 10: 1 f at ref, internal reference settling to 0.5lsb. t ypical operating characteristics (v dd = +3.0v (max1108), v dd = +5.0v (max1109); external conversion mode; f sclk = 500khz; 50ksps; external reference; 1 f at ref; t a = +25 c; unless otherwise noted.) 200 0 0 6 supply current vs. supply voltage 40 20 180 160 max1108/09-01 supply voltage (v) supply current ( m a) 1 2 3 4 5 140 120 100 80 60 d out = 10101010 max1108 (2.7v to 5.5v) max1109 (4.5v to 5.5v) internal reference c load = 47pf c load = 10pf 200 0 -40 100 supply current vs. temperature 40 20 180 160 max1108/09-02 temperature (?) supply current ( m a) -20 0 20 40 60 80 140 120 100 80 60 v dd = 5v v dd = 3v d out = 10101010 c load = 10pf internal reference 0.50 0 2.5 5.5 shutdown supply current vs. supply voltage 0.10 0.05 0.45 0.40 max1108/09-03 supply voltage (v) shutdown current ( m a) 3.0 3.5 4.0 4.5 5.0 0.35 0.30 0.25 0.20 0.15
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v dd = +3.0v (max1108), v dd = +5.0v (max1109); external conversion mode; f sclk = 500khz; 50ksps; external reference; 1 f at ref; t a = +25 c; unless otherwise noted.) 0.5 -0.5 2.5 5.5 offset error vs. supply voltage -0.3 -0.4 0.4 0.3 max1108/09-04 supply voltage (v) offset error (lsb) 3.0 3.5 4.0 4.5 5.0 0.2 0.1 0 -0.1 -0.2 0.5 -0.5 -40 100 offset error vs. temperature -0.3 -0.4 0.4 0.3 max1108/09-05 temperature (?) offset error (lsb) -20 0 20 40 60 80 0.2 0.1 0 -0.1 -0.2 0.20 -0.20 0 5.0 offset error vs. reference voltage -0.10 -0.15 0.15 0.10 max1108/09-06 reference voltage (v) offset error (lsb) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.05 0 -0.05 0.5 -0.5 2.5 5.5 gain error vs. supply voltage -0.3 -0.4 0.4 0.3 max1108/09-07 supply voltage (v) gain error (lsb) 3.0 3.5 4.0 4.5 5.0 0.2 0.1 0 -0.1 -0.2 0.3 -0.3 2.5 5.5 integral nonlinearity vs. supply voltage -0.1 -0.2 0.2 max1108/09-10 supply voltage (v) inl (lsb) 3.0 3.5 4.0 4.5 5.0 0.1 0 1.0 -1.0 -40 100 gain error vs. temperature -0.6 -0.8 0.8 0.6 max1108/09-08 temperature (?) gain error (lsb) -20 0 20 40 60 80 0.4 0.2 0 -0.2 -0.4 1.0 -1.0 0 5.0 gain error vs. reference voltage -0.4 -0.6 -0.8 0.8 0.6 max1108/09-09 reference voltage (v) gain error (lsb) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.4 0 0.2 -0.2 0.5 -0.5 0 300 differential nonlinearity vs. code -0.1 0 -0.3 -0.4 -0.2 0.4 0.3 max1108/09-11 digital code dnl (lsb) 50 100 150 200 250 0.1 0.2 0.5 -0.5 2.5 5.5 differential nonlinearity vs. supply voltage -0.2 -0.3 -0.4 0.4 0.3 max1108/09-12 supply voltage (v) dnl (lsb) 3.0 3.5 4.0 4.5 5.0 0.2 0.1 0 -0.1
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs _______________________________________________________________________________________ 9 0.5 -0.5 0 300 integral nonlinearity vs. code -0.1 0 -0.3 -0.4 -0.2 0.4 0.3 max1108/09-13 digital code inl (lsb) 50 100 150 200 250 0.1 0.2 20 -100 0 30 fft plot -60 -80 0 max1108/09-14 frequency (khz) amplitude (db) 5 10 15 20 25 -20 -40 f ch_ = 9997hz, 2vp-p f sample = 53.25khz 21.0 18.0 0 6 conversion time vs. supply voltage 19.0 18.5 20.5 max1108/09-15 supply voltage (v) conversion time( m s) 1 2 3 4 5 20.0 19.5 internal conversion mode t ypical operating characteristics (continued) (v dd = +3.0v (max1108), v dd = +5.0v (max1109); external conversion mode; f sclk = 500khz; 50ksps; external reference; 1 f at ref; t a = +25 c; unless otherwise noted.) pin description sampling analog inputs ch0, ch1 2, 3 reference voltage for analog-to-digital conversion (internal or external reference). reference input for external reference. bypass internal reference with 1 f capacitor to gnd. ref 5 ground gnd 4 active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. cs 7 serial data output. data is clocked out on the falling edge of sclk. high impedance when cs is high. dout 9 serial data input. data is clocked in at the rising edge of sclk. din 8 common reference for analog inputs. sets zero-code voltage in single-ended mode. must be stable to 0.5lsb during conversion. com 6 serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. sclk 10 pin positive supply voltage v dd 1 function name 25 15 -40 100 conversion time vs. temperature 18 17 16 24 23 max1108/09-16 temperature (?) conversion time ( m s) -20 0 20 40 60 80 22 21 20 19 internal conversion mode v dd = 3v v dd = 5v 1.0010 0.9980 -40 100 normalized reference voltage vs. temperature 0.9990 0.9985 1.0005 max1108/09-17 temperature (?) reference voltage (v) -20 0 20 40 60 80 1.0000 0.9995 0 -100 0 25 channel-to-channel crosstalk vs. frequency -70 -80 -90 -10 -20 max1108/09-18 frequency (khz) crosstalk (db) 5 10 15 20 -30 -40 -50 -60 v ch_off = v refp-p
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 10 ______________________________________________________________________________________ _______________ detailed description the max1108/max1109 analog-to-digital converters (adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to an 8-bit digital output. a flexible serial interface provides easy interface to microproces - sors ( ps). no external hold capacitors are required. all of the max1108/max1109 operating modes are soft - ware-configurable: internal or external reference, inter - nal or external conversion clock, single-ended unipolar or pseudo-differential unipolar/bipolar conversion, and power down (table 1). analog inputs track/hold the input architecture of the adcs is illustrated in the equivalent-input circuit of figure 4 and is composed of the t/h, the input multiplexer, the input comparator, the switched capacitor dac, the reference, and the auto- zero rail. the analog-inputs configuration is determined by the control-byte through the serial interface as shown in table 2 (see modes of operation section and table 1). the eight modes of operation include single-ended, pseudo-differential, unipolar/bipolar, and a v dd moni - toring mode. during acquisition and conversion, only one of the switches in figure 4 is closed at any time. the t/h enters its tracking mode on the falling clock edge after bit 4 (sel0) of the control byte has been shifted in. it enters its hold mode on the falling edge after the bit 2 (i/eref) of the control byte has been shifted in. for example, if ch0 and com are chosen (sel2 = sel1 = sel0 = 1) for conversion, ch0 is defined as the sampled input (si), and com is defined as the refer - ence input (ri). during acquisition mode, the ch0 switch and the t/h switch are closed, charging the v dd 3k c load dgnd dout c load dgnd 3k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 1. load circuits for enable time v dd 3k c load dgnd dout c load dgnd 3k dout a) v oh to high-z b) v ol to high-z figure 2. load circuits for disable time v dd i/o sck (sk) mosi (so) miso (si) v ss dout din sclk cs com gnd v dd ch1 1 m f 0.1 m f 1 m f ch0 analog inputs max1108 max1109 cpu v dd ref figure 3. typical operating circuit ch0 com v dd / 2 gnd ch1 ref gnd c hold capacitive dac comparator 18pf r in 6.5k autozero rail track hold figure 4. equivalent input circuit
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs ______________________________________________________________________________________ 11 holding capacitor c hold through r in . at the end of acquisition the t/h switch opens and c hold is con - nected to com, retaining charge on c hold as a sam - ple of the signal at ch0, and the difference between ch0 and com is the converted signal. once conver - sion is complete, the t/h returns immediately to its tracking mode. this procedure holds for the different combinations summarized in table 2. the time available for the t/h to acquire an input signal (t acq ) is determined by the clock frequency, and is 1 s at the maximum clock frequency of 2mhz. the acquisi - tion time is also the minimum time needed for the signal to be acquired. it is calculated by: t acq = 6(r s + r in )18pf where r in = 6.5k , r s = the source impedance of the input signal, and t acq is never less than 1 s. note that source impedances below 2.7k do not significantly affect the ac performance of the adc at the maximum clock speed. if the input-source imped - ance is higher than 3k , the clock speed must be reduced accordingly. pseudo-differential input the max1108/max1109 input configuration is pseudo- differential to the extent that only the signal at the sam - pled input (si) is stored in the holding capacitor (c hold ). the reference input (ri) must remain stable within 0.5lsb ( 0.1lsb for best results) in relation to gnd during a conversion. sampled input and refer - ence input configuration is determined by bit6?it4 (sel2?el0) of the control byte (table 2). if a varying signal is applied at the selected reference input, its amplitude and frequency need to be limited. the following equations determine the relationship between the maximum signal amplitude and its fre - quency to maintain 0.5lsb accuracy: assuming a sinusoidal signal at the reference input the maximum voltage variation is determined by: a 60hz signal at ri with an amplitude of 1.2v will gener - ate a 0.5lsb of error. this is with a 35 s conversion time (maximum t conv in internal conversion mode) and a reference voltage of +4.096v. when a dc reference voltage is used at ri, connect a 0.1 f capacitor to gnd to minimize noise at the input. the input configuration selection also determines unipolar or bipolar conversion mode. the common- mode input range of ch0, ch1, and com is 0 to +v dd . in unipolar mode, full scale is achieved when (si - ri) = v ref ; in bipolar mode, full scale is achieved when ? (si - ri ) ? = v ref / 2. in unipolar mode, si must be higher than ri; in bipolar mode, si can span above and below ri provided that it is within the common-mode range. conversion process the comparator negative input is connected to the auto- zero rail. since the device requires only a single supply, the zero node at the input of the comparator equals v dd /2. the capacitive dac restores node zero to have 0v difference at the comparator inputs within the limits of 8-bit resolution. this action is equivalent to transfer - ring a charge of 18pf(v in+ - v in- ) from c hold to the binary-weighted capacitive dac which, in turn, forms a digital representation of the analog-input signal. input voltage range internal protection diodes that clamp the analog input to v dd and agnd allow the channel input pins (ch0, ch1, and com) to swing from (agnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conver - sions, the inputs must not exceed (v dd + 50mv) or be less than (gnd - 50mv). if the analog input voltage on an ?ff?channel exceeds 50mv beyond the supplies, the current should be limited to 2ma to maintain conversion accuracy on the ?n?channel. the max1108/max1109 input range is from 0 to v dd ; unipolar or bipolar conversion is available. in unipolar mode, the output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. the reference input-voltage range at ref is from 1v to (v dd + 50mv.) input bandwidth the adc? input tracking circuitry has a 1.5mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre - quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. serial interface the max1108/max1109 have a 4-wire serial interface. the cs , din, and sclk inputs are used to control the device, while the three-state dout pin is used to access the result of conversion. max dv dt 2 f v 1 lsb t v 2 t ri ri conv ref 8 conv = = p v v sin(2 ft) ri ri = p
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 12 ______________________________________________________________________________________ the serial interface provides easy connection to micro - controllers with spi, qspi and microwire serial inter - faces at clock rates up to 2mhz. for spi and qspi, set cpol = cpha = 0 in the spi control registers of the microcontroller. figure 5 shows the max1108/max1109 common serial-interface connections. digital inputs the logic levels of the max1108/max1109 digital input are set to accept voltage levels from both +3v and +5v systems, regardless of the supply voltages. input data (control byte) is clocked in at the din pin on the rising edge of serial clock (sclk). cs is the standard chip- select signal which enables communication with the device. sclk is used to clock data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. digital output output data is read on the rising edge of sclk at dout, msb first (d7). in unipolar input mode, the out - put is straight binary. for bipolar input mode, the output is twos-complement (see transfer function section). dout is active when cs is low and high impedance when cs is high. dout does not accept external volt - ages greater than v dd . in external-clock mode, data is clocked out at the maximum clock rate of 500khz while conversion is in progress. in internal-clock mode, data can be clocked out at up to 2mhz clock rate. modes of operation the max1108/max1109 feature single-ended or pseu - do-differential operation in unipolar or bipolar configu - ration. the device is programmed through the input control-byte at the din pin of the serial interface (table 1). table 2 shows the analog-input configuration and table 3 shows the input-voltage ranges in unipolar and bipolar configuration. how to start a conversion a conversion is started by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the max1108/max1109? internal shift register. after cs falls, the first arriving logic ??bit at din defines the msb of the control byte. until this first start bit arrives, any number of logic ??bits can be clocked into din with no effect. table 1 shows the con - trol-byte format. using the typical operating circuit (figure 3), the sim - plest software interface requires two 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and one 8-bit transfer to clock out the 8-bit conversion result). figure 6 shows a single-conversion timing diagram using external clock mode. clock modes the max1108/max1109 can use either an external ser - ial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the devices. bit 3 of control-byte (i/eclk) programs the clock mode. figure 8 shows the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. in this mode the clock frequency must be between 50khz and 500khz. single-conver - sion timing using an external clock begins with a falling edge on cs . when this occurs, dout leaves the high impedance state and goes low. the first ??clocked into din by sclk after cs is set low is considered as the start bit. the next seven clocks latch in the rest of the control byte. on the falling edge of the fourth clock, track mode is enabled, and on the falling edge of the sixth clock, acquisition is complete and conversion is cs sclk dout i/o sck miso +3v ss a) spi cs sclk dout cs sck miso +3v ss b) qspi max1108 max1109 max1108 max1109 max1108 max1109 cs sclk dout i/o sk din mosi din mosi din so si c) microwire figure 5. common serial-interface connections
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs ______________________________________________________________________________________ 13 table 1. control byte format table 2. conversion configuration table 3. full- and zero-scale voltages * ri = reference input (table 2) start sel2 sel1 sel0 i/eclk i/eref refshdn shdn bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) name i/eref 2 bit 1 = internal reference, 0 = external reference. internal reference selects +2.048v (max1108) or +4.096v (max1109), or an external reference can be applied to the ref pin. description i/eclk 3 start 1 = external clock, 0 = internal clock. the sar can be driven by the internal oscillator, or with the sclk signal. shdn 0 (lsb) 7 (msb) 1 = operational, 0 = power down. for a full power down set refshdn = shdn = 0. (see power- down mode section.) the first logic ??bit after cs goes low defines the beginning of the control byte. sel2 sel1 sel0 6 5 4 selects the mode of operation (table 2). refshdn 1 1 = operational (if i / eref = 1), 0 = reference shutdown. when using an external reference, power consumption can be minimized by powering down the internal reference separately (i / eref = 0). refshdn must be set to 0 when shdn = 0. unipolar mode ri* ri - v ref / 2 zero scale ri + v ref ri ri + v ref / 2 negative full scale full scale zero scale bipolar mode positive full scale sel2 1 1 1 1 sel1 sampled input (si) sel0 0 1 ch1 ch0 conversion mode reference input (ri) com com unipolar unipolar 1 0 1 0 1 ch1 ch0 0 gnd gnd unipolar unipolar 0 0 0 1 1 ch1 ch0 1 com com bipolar bipolar 0 0 0 0 1 v dd / 2 ch0 0 gnd ch1 unipolar bipolar
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 14 ______________________________________________________________________________________ initiated. the msb successive-approximation bit deci - sion is made on the rising edge of the seventh sclk. on the falling edge of the eighth sclk, the msb is clocked out on the dout pin; on each of the next seven sclk falling edges, the remaining bits of conver - sion are clocked out. zeros are clocked out on dout after the lsb has been clocked out, until cs is dis - abled. then dout becomes high impedance and the part is ready for another conversion (figure 6). the conversion must complete in 1ms, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the serial-clock fre - quency is less than 50khz, or if serial-clock interrup - tions could cause the conversion interval to exceed 1ms. internal clock internal clock mode frees the p from the burden of running the sar conversion clock. this allows the con - version results to be read back at the processor? con - venience, at any clock rate up to 2mhz. an internal register stores data when the conversion is in progress. on the falling edge of the fourth sclk, track mode is enabled, and on the falling edge of the eighth sclk, acquisition is complete and internal con - version is initiated. the internal 400khz clock com - pletes the conversion in 20 s typically (35 s max), at which time the msb of the conversion is present at the dout pin. the falling edge of sclk clocks the remain - ing data out of this register at any time after the conver - sion is complete (figure 8). cs sclk din dout 1 4 8 12 16 20 start sel2 msb lsb sel1 sel0 i/eclk i/eref ref shdn shdn d7 msb lsb d6 d5 d4 d3 d2 d1 d0 idle idle t conv t acq a/d state figure 6. single conversion timing, external clock mode cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 7. detailed serial-interface timing
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs ______________________________________________________________________________________ 15 cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the max1108/max1109 and three-states dout, but it does not adversely affect an internal clock-mode conversion already in progress. in this mode, data can be shifted in and out of the max1108/max1109 at clock rates up to 2mhz, provid - ed that the minimum acquisition time (t acq ) is kept above 1 s. quick look to quickly evaluate the max1108/max1109? analog performance, use the circuit of figure 9. the device requires a control byte to be written to din before each conversion. tying cs to gnd and din to v dd feeds in control bytes of ffh. in turn, this triggers single-ended, unipolar conversions on ch0 in relation to com in external clock mode without powering down between conversions. apply an external 50khz to 500khz clock cs sclk din dout 1 4 8 start sel2 sel1 sel0 i/eref i/eclk ref shdn shdn d7 d6 d5 d4 d3 d2 d1 d0 t acq idle idle a/d state 10 14 18 t conv 35 m s max figure 8. single conversion timing, internal clock mode 1? 0.1? v dd gnd cs sclk din dout v dd 0.01? ch0 com ref c1 1? analog input oscilloscope ch1 ch2 5 m s/div *conversion result = 10101010 max1108 max1109 v supply 500khz oscillator dout* sclk msb lsb figure 9. quick-look schematic
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs 16 ______________________________________________________________________________________ to the sclk pin; varying the analog input alters the result of conversion that is clocked out at the dout pin. a total of 10 clock cycles is required per conversion. data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. acquisition starts on the falling edge of the fourth sclk and lasts for two sclks in external clock mode or four sclks in internal clock mode. conversion starts imme - diately after acquisition is completed. the start bit is defined as: the first high bit clocked into din with cs low any time the converter is idle; e.g., after v dd is applied. or in external clock mode, the first high bit clocked into din after the bit 5 (d5) of a con - version in progress is clocked onto the dout pin. or in internal clock mode, the first high bit clocked into din after the bit 4 (d4) is clocked onto the dout pin. the max1108/max1109 can run at a maximum speed of 10 clocks per conversion. figure 10 shows the serial- interface timing necessary to perform a conversion every 10 sclk cycles in external clock mode. many microcontrollers require that conversions occur in multiples of 8 sclk clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the max1108/max1109. figure 11 shows the serial-inter - face timing necessary to perform a conversion every 16 sclk cycles in external clock mode. sclk din dout cs s control byte 0 control byte 1 s conversion result 0 d7 d5 d0 d7 d5 d0 d7 conversion result 1 control byte 2 s 1 8 10 1 10 1 10 1 s t acq t acq t acq idle a/d state t conv t conv t conv figure 10. continuous conversion, external clock mode, 10 clocks/conversion timing sclk din dout cs s control byte 0 control byte 1 s conversion result 0 d7 d0 d7 d0 conversion result 1 s 1 8 17 25 figure 11. continuous conversion, external clock mode, 16 clocks/conversion timing
in external clock mode, if cs is toggled before the cur - rent conversion is complete, the current conversion is terminated, and the next high bit clocked into din is recognized as a new start bit. this can be useful in extending acquisition time by selecting conversion on the same channel with the second control byte (double- clocking mode), effectively extending acquisition to 6 sclks. this technique is ideal if the analog input source has high impedance, or if it requires more than 1 s to settle; it can also be used to allow the device and the reference to settle when using power down- modes (see power-down modes section). __________ applications infor mation battery monitoring mode this mode of operation samples and converts the mid- supply voltage, v dd / 2, which is internally generated. set sel2 = sel1 = sel0 = 0 in the control byte to select this configuration. this allows the user to monitor the condition of a battery providing v dd . the reference voltage must be larger than v dd / 2 for this mode of operation to work properly. from the result of conver - sion (code), v dd is determined as follows: v dd = code v ref / 128. power-on configuration when power is first applied, the max1108/max1109? reference is powered down and shdn is not enabled. the device needs to be configured by setting cs low and writing the control byte. conversion can be started within 20 s if an external reference is used. when using the internal reference, allow 12ms for the reference to settle. this is done by first performing a configuration conversion to power up the reference and then per - forming a second conversion once the reference is set - tled. no conversions should be considered correct until the reference voltage (internal or external) has stabi - lized. power-down modes to save power, place the converter into low-current power-down mode between conversions. minimum power consumption is achieved by programming refshdn = 0 and shdn = 0 in the input control byte (table 4). when software power-down is asserted, it becomes effective only after the conversion. if the con - trol byte contains refshdn = 0, then the reference will turn off at the end of conversion. if shdn = 0, then the chip will power-down at the end of conversion (in this mode i/eref or refshdn should also be set to zero). table 4 lists the power-down modes of the max1108/ max1109. the first logical 1 clocked into din after cs falls powers up the max1108/max1109 (20 s required for the device to power up). the reference is powered up only if internal reference was selected during the previous conversion. when the reference is powered up after being disabled, consider the settling time before using the result of conversion. typically, 12ms are required for the reference to settle from a discharge state; less time may be considered if the external capacitor is not discharged completely when exiting shutdown. in all power-down modes, the interface remains active and conversion results may be read. use the double clock - ing technique described in the data framing section to allow more time for the reference to settle before start - ing a conversion after short power-down. voltage reference the max1108/max1109 operate from a single supply and feature a software-controlled internal reference of +2.048v (max1108) and +4.096v (max1109). the device can operate with either the internal reference or an external reference applied at the ref pin. see the power-down modes and modes of operation sections for detailed instructions on reference configuration. the reference voltage determines the full-scale range: in unipolar mode, the input range is from 0 to v ref ; in bipolar mode, the input range spans ri v ref / 2 with ri = v ref / 2. max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs ______________________________________________________________________________________ 17 table 4. power-down modes of the max1108/max1109 1 bit 2?it 0 of control byte 1 1 0 1 1 1 0 0 0 1 x 1 0 0 1 0 x refshdn i/eref shdn operating mode device active; internal refer - ence powered down after con - version, powered up at next start bit. device active/internal reference active device and internal reference powered down after conversion, powered up at next start bit. device active/external reference mode reserved. do not use. device powered down after each conversion, powered up at next start bit. external reference mode. x = don? care
max1108/max1109 external reference to use an external reference, set bit 2 (i/eref) and bit 1 ( refshdn ) of control byte to 0 and connect the external reference (v ref between 1v and v dd ) directly at the ref pin. the dc input impedance at ref is extremely high, consisting of leakage current only (typi - cally 10na). during a conversion, the reference must be able to deliver up to 20 a average load current and have an output impedance of 1k or less at the conver - sion clock frequency. if the reference has higher output impedance or is noisy, bypass it close to the ref pin with a 0.1 f capacitor. max1109 has an internal refer - ence of +4.096v. to use the device with supply volt - ages below 4.5v, external reference mode is required. with an external reference voltage of less than +2.048v (max1108) or +4.096v (max1109) at ref, the increase in the ratio of the rms noise to the lsb value (fs / 256) results in performance degradation and decreased dynamic range. internal reference to use the internal reference, set bit 2 (i/eref) and bit 1 ( refshdn ) of the control byte to 1 and bypass ref with a 1 f capacitor to ground. the internal reference can be powered down after a conversion by setting bit 1 ( ref - shdn ) of the control byte to 0. when using the internal reference, use max1108 and max1109 with supply volt - age below 4.5v and above 4.5v, respectively. transfer function table 4 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 12a depicts the nominal, unipolar i/o transfer function, and figure 12b shows the bipolar i/o transfer function. the zero scale is deter - mined by the input selection setting and is either com, gnd, or ch1. code transitions occur at integer lsb values. output coding is straight binary for unipolar operation and two? complement for bipolar operation. with a +2.048v reference, 1lsb = 8mv (v ref / 256). layout, grounding, and bypassing for best performance, use printed circuit boards. wire- wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi - tal (especially clock) lines parallel to one another or run digital lines underneath the adc package. figure 13 shows the recommended system-ground connections. a single-point analog ground (star-ground point) should be established at the a/d ground. connect all analog grounds to the star ground. no digi - tal-system ground should be connected to this point. the ground return to the power supply for the star ground should be low impedance and as short as pos - sible for noise-free operation. high-frequency noise in the v dd power supply may affect the comparator in the adc. bypass the supply to the star ground with 0.1 f and 1 f capacitors close to the v dd pin of the max1108/max1109. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 resistor can be connected to form a lowpass filter. single-supply , low-power , 2-channel, serial 8-bit adcs 18 ______________________________________________________________________________________ output code full-scale transition 11111111 11111110 11111101 00000011 00000010 00000001 00000000 1 2 3 0 fs fs - 1lsb fs = v ref + com 1lsb = v ref 256 input voltage (lsb) (com) figure 12a. unipolar transfer function 01111111 output code 01111110 00000010 00000001 00000000 11111111 11111110 11111101 10000001 10000000 -fs com input voltage (lsb) +fs - 1 lsb 2 +fs = v ref + com 2 -fs = -v ref + com 2 com = v ref 2 1lsb = v ref 256 figure 12b. bipolar transfer function
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs ______________________________________________________________________________________ 19 gnd +3v/+5v system power supplies v dd dgnd v dd com 1 m f 10 w 0.1 m f gnd digital circuitry max1108 max1109 figure 13. power-supply connections chip infor mation transistor count: 2373
max1108/max1109 single-supply , low-power , 2-channel, serial 8-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. package infor mation 10lumaxb.eps

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